The main goal is to familarize students about the the design and analysis of the operation of digital gates. Design and implementation of combinational and sequential logic circuits. Concepts of Boolean algebra, Karnaugh maps, flip-flops, registers, and counters along with various logic families and comparison of their behavior and characteristics.
LIST OF CLOs
CLO |
Domain Level |
CLOs |
PLO |
CLO:1
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P1 |
Describe and illustrate fundamentals of Digital Logic Design |
1 |
CLO:2
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P3 |
Demonstrate the acquired knowledge to apply techniques related to the design and analysis of digital logic circuits |
2 |
CLO:3
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P4 |
Design and Implement small-scale logic circuit (basic, combinational & sequential digital circuit) for desired output. |
3 |
CLO:4 |
A2 |
Function individually as well as a team. |
9 |
MAPPING OF CLOS WITH PLOs
PLOs |
CLO 1 |
CLO 2 |
CLO 3 |
CLO4 |
CLO5 |
CLO6 |
CLO7 |
CLO8 |
CLO9 |
PLO:1 (Engineering Knowledge) |
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PLO:2 (Problem Analysis) |
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PLO:3 (Design Development of Solutions) |
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PLO:4 (Investigation) |
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PLO:5 (Modern Tool Usage) |
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PLO:6 (Engineer & Society) |
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PLO:7 (Environment and Sustainability) |
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PLO:8 (Ethics) |
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PLO:9 (Individual & Team Work) |
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PLO:10 (Communication) |
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PLO:11 (Project Management) |
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PLO:12 (Life Long Learning) |
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LIST OF EXPERIMENTS
Lab No. |
Title |
1 |
TO STUDY BASIC LOGIC GATE INTEGRATED CIRCUITS AND VERIFICATION OF THEIR TRUTH TABLES |
2 |
IMPLEMENTATION OF THE UNIVERSALITY OF NAND AND NOR GATES |
3 |
IMPLEMENTATION OF THE HALF ADDER AND FULL ADDER |
4 |
IMPLEMENTATION OF THE 4-BIT PARALLEL ADDER USING IC 74283 |
5 |
IMPLEMENT OF THE HALF AND FULL SUBTRACTOR |
6 |
IMPLEMENTATION OF THE CODE CONVERTERS USING GATES |
7 |
TO IMPLEMENT THE ENCODER AND DECODER USING IC 74138 & 74148 |
8 |
IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER USING IC74151& IC74138 |
9 |
VERIFICATION OF LATCH AND FLIP FLOP OPERATION USING GATES AND FLIP FLOP’S IC |
10 |
COUNTERS |
11 |
IMPLEMENTATION OF SERIES AND PARALLEL REGISTERS |
12 |
STUDY OF THE COMMANDS OF SHIFT AND ROTATE INSTRUCTIONS |
13 |
ALU DESIGN IN VERILOG. |
14 |
SEMESTER PROJECT EVALUATION |