Course Syllabus

                                                                                                         ET-213: Digital Electronics (DE)

                                                                                                        Semester / Session: 3rd/Fall-2020

 

 

Instructor:                  Engr. SaadUllah

                                    Room:  3rd Floor

                                    Phone: +92-333-9930721

                                    E-mail: [email protected]

 

Office Hours:               08:00 hrs to 16:00 hrs

                                                                                                           

Course TA:                  N.A.

 

Course Description:     The aim of the course is to introduce to the students' topics that include combinational and sequential circuit analysis and design, digital circuit design optimization methods using random logic gates, multiplexers, decoders, registers, and counters. One of the main goals of this course is to teach students the basic concepts in conventional digital design and to clearly demonstrate the way in which digital circuits are designed and analyzed nowadays.  

 

Catalog Data:              Course Code:                            ET-213

                                    Course Title:                             Digital Electronics (DE)

                                    Credit Hours:                            3+1 (4)

                                    Course Designation:                  Core

                                    No of Sessions per week:           1 (Total 16 sessions)

                                    Session Duration:                     180 min

 

Catalog Description:    ET-213 Digital Electronics, Credits (3)

                                      Number Systems, Boolean Algebra, Logic Simplification, Combinational Logic, Sequential Logic, Latches, Flip-Flops and their applications. Adders, Multiplexers, Counters, Shift Registers, and simple Arithmetic Logic Unit (ALU). Design and implementation of combinational circuits in Verilog, Introduction to FPGA.

 

Prerequisite:                Nil

 

                                       Prerequisites by

                                       Topics:                         NIL

 

Co-requisite:                NIL

 

Textbook:                     Morris Mano and Micheal D. Ciletti, “Digital Design with an                                                

                                      introduction to the Verilog HDL”, Prentice Hall, 5th Edition.

 

 

 

Program Learning

Outcome:                     This course is designed in conjunction with the following PLOs.

 

PLO 1. Engineering Knowledge: An ability to apply knowledge of mathematics, science, engineering fundamentals and an engineering specialization to the solution of complex engineering problems.

 

PLO 2. Problem Analysis: An ability to identify, formulate, research literature, and analyze complex engineering problems reaching substantiated conclusions using first principles of mathematics, natural sciences and engineering sciences.

 

PLO   3.   Design/Development of Solutions: An ability to design solutions for complex engineering problems and design systems, components, or processes that meet specified needs with appropriate consideration for public health and safety, cultural, societal, and environmental considerations.

                                   

                                      

Course Learning Outcome (CLO):

Upon successful completion of this course, the student will be able to:

 

CLO No

Course Learning Outcome (CLO) Statements

Taxonomy Domain

Mapped PLO

Assessment

CLO-1

Identify and explain fundamental concepts of digital logic design including basic and universal gates, number systems, and binary coded systems, basic components of combinational and sequential circuits.

 

                                C2

                      (Understanding)

 

            PLO 1

           A1, MP1, Q1

CLO-2

Use the acquired knowledge to apply techniques related to the design and analysis of digital electronic circuits including Boolean algebra and multi-variable Karnaugh map methods.

 

                                  C3

                           (Applying)

          PLO 2

     A2, MP2, Q2, FP1

CLO-3

Construct small-scale combinational and sequential logic circuits (includes latches, flip-flops, registers & counters)

                                  C3

                            (Applying)

          PLO 3

            A3, Q3, FP2

 

NOTE:  Domain:           C = Cognitive,            

Assessment Tool: A = Assignment, Q = Quiz, M = Midterm, F = Final (P1: Part1)

 

 

Course Professional Outcome/ Industrial Usage:                         

 

                             This course is an introductory course on Digital Logic & Design. It is designed for students in engineering and other related fields. The purpose is to make students familiar with                                     modern hierarchy of digital hardware and explain them the state-of-the-art computer hardware design methodologies.

 

 

 

 

 

Course Outline and

Sessions Breakdown:  

                                    I. Number Systems & Boolean Algebra (CLO-1)

                                    (08 Sessions)

                                    Digital System, Binary Numbers, Number base Conversions, Octal and                                 Hexadecimal Numbers, Compliments, Signed Binary Number, Binary                                  Codes, Gray Code, BCD System, Binary Addition, Subtraction, and                             Multiplication. Introduction. basic definitions, Axiomatic definition                               of Boolean Algebra, Basic Theorems & Postulates. Boolean Function,                           Boolean laws and reduction, Conical Standard from and Digital Logic                         Gates.

 

                                    II Gate level Minimization (CLO 2,3)

                                    (08 Sessions)

                                    K-map (two variable, three variable and four variable), Prime                                                 Implicants, Sum of Product (SOP) & Product of Sum (POS)                                      Simplification. K-map Methods, NAND & NOR implementation,                                              Two level Implementations, & Don't Care Condition.

 

                                    III.  Combinational Logic Circuit, Design (CLO 3)

                                    (8 Sessions)

                                    Combinational Logic Circuit, Analysis Procedure, Design Procedure of                                       Combinational Logic Circuit. Binary Adder- Subtractors &Full Adder.                               Magnitude Comparator, Decoder, Encoder.          Implementation of full                                    adder with a decoder. Multiplexers and De-multiplexer.

 

                                    IV.  Synchronous Sequential Logic & Register & Counters:

                                    (08 Sessions) (CLO 3)

                                    Design and Analysis Procedure of Sequential circuits, Introduction                            sequential circuits, storage element: Latches. Registers, Shift Registers,                                   Synchronous & A-Synchronous counters.

 

Computer Usage:         Verilog HDL (ModelSim).

 

Projects /

 

Design Activities:         Students will be asked to design/solve complex engineering problem

 

 

Evaluation Criteria:    1. Assignments                         15%

2. Quizzes                                 15%

3. Mid-Term Exam                    20%

4. Final Exam                            50%

 

 

 

 

 

COURSE DISTRIBUTION ON WEEKLY BASIS

 

Weeks

Topics

Quiz/ Assignment

 
 

WEEK 01

 

Introduction and brief overview:

  • Number Systems
  • Digital System,
  • Binary Numbers
  •  Number base Conversions, (Decimal, Binary, Octal and Hexadecimal Numbers)

 

 

WEEK 02 TO WEEK 04

 

  • Compliments
  • Signed Binary Number
  • Binary Codes, Gray Code, BCD System, Binary
  • Addition, Subtraction and Multiplication
  • Boolean Algebra, Axiomatic Definition of Boolean Algebra,
  • Basic Theorems & Postulates
  • Boolean Function, Boolean laws and reductio
  • Conical Standard From
  • Digital Logic Gates

 

 

WEEK 05 TO WEEK 06

 

 Gate level Minimization

  • K-map (two variable, three variable and four variable)
  •  Prime Implicants 
  •  Sum of Product (SOP)
  •  Product of Sum (POS) Simplification.

Quiz 1

 

WEEK 07 TO WEEK 08

 

  • K-map Methods
  •  NAND & NOR implementation
  • Two level Implementations,
  • Don't Care Condition
  • Introduction to HDL (Hardware Description Language)

Assignment 1

 

WEEK 09

 

Mid Semester Exam

 

 

 

WEEK 10

 

Introduction to Combinational Logic Circuit, Analysis Procedure, Design Procedure of Combinational Logic Circuit. Combinational Logic Model using Verilog (ModelSim

 

 

WEEK 11

 

Binary Adder- Subtractors (Half Adder, Full Adder,) and 4 Bit parallel adder.  Verilog HDL Implementation of Half Adder &Full Adder

 

 

WEEK 12

 

 Magnitude Comparator, Decoder, Encoder, Implementation of full adder with a decoder. Multiplexers and De-multiplexer, HDL Model of Combinational Circuit.

Quiz 2

 

WEEK 13

 

Synchronous Sequential Logic:

Design and Analysis Procedure of Sequential circuits, Introduction sequential circuits, storage element: Latches (SR Latch, D Latch) Flip-Flops (RS Flip Flop, Edge-Triggered D Flip Flop).

Assignment 2

 

WEEK 14

 

(JK Flip Flop, T Flip Flop), derive state equations from truth table state table / state equation and state diagram. Analysis & design procedure of clocked sequential circuits state reduction.  Design HDL Model of Sequential Circuits including latches, flip flops.

 

 

Week 15

Register & Counters:

Registers, Shift Registers (SISO, SIPO, PISO, PIPO and Universal Shift Register).

 

 

 

WEEK 16

 

Counters,

 Ripple Counters, BCD Ripple counters, Synchrony Counters and other counters, designing of 2 bit/ 3 bit synchronous up/down counters.

 

Quiz 3

Assignment 3

 

WEEK 17

Introduction to FPGA.

HDL for Registers and Counters (using Verilog HDL (ModelSim)).

 

 

WEEK 18

 

End Semester Exam

 

 

 

 

Policies

 

  1. No makeup tests or quizzes, except in case of emergency, e.g. illness and accident. For makeup tests, medical certificate is required, and the instructor must be notified in advance of the test.
  2. No late assignment will be accepted.

 

Course Material