Instructor:                  Engr. SaadUllah

                                    Room:  3rd Floor

                                    Phone: +92-333-9930721

                                    E-mail: [email protected]

Office Hours:               08:00 hrs to 16:00 hrs

Course TA:                  N.A.

Course Description:     The aim of the course is to introduce to the students' topics that include combinational and sequential circuit analysis and design, digital circuit design optimization methods using random logic gates, multiplexers, decoders, registers, and counters. One of the main goals of this course is to teach students the basic concepts in conventional digital design and to clearly demonstrate the way in which digital circuits are designed and analyzed nowadays.  

Catalog Data:              Course Code:                            ET-213

                                    Course Title:                             Digital Electronics (DE)

                                    Credit Hours:                            3+1 (4)

                                    Course Designation:                  Core

                                    No of Sessions per week:           1 (Total 16 sessions)

                                    Session Duration:                     180 min

Catalog Description:    ET-213 Digital Electronics, Credits (3)

                                      Number Systems, Boolean Algebra, Logic Simplification, Combinational Logic, Sequential Logic, Latches, Flip-Flops and their applications. Adders, Multiplexers, Counters, Shift Registers, and simple Arithmetic Logic Unit (ALU). Design and implementation of combinational circuits in Verilog, Introduction to FPGA.

Prerequisite:                Nil

                                       Prerequisites by

                                       Topics:                         NIL

Co-requisite:                NIL

Textbook:                     Morris Mano and Micheal D. Ciletti, “Digital Design with an                                                

                                      introduction to the Verilog HDL”, Prentice Hall, 5th Edition.

Program Learning

Outcome:                     This course is designed in conjunction with the following PLOs.

PLO 1. Engineering Knowledge: An ability to apply knowledge of mathematics, science, engineering fundamentals and an engineering specialization to the solution of complex engineering problems.

PLO 2. Problem Analysis: An ability to identify, formulate, research literature, and analyze complex engineering problems reaching substantiated conclusions using first principles of mathematics, natural sciences and engineering sciences.

PLO   3.   Design/Development of Solutions: An ability to design solutions for complex engineering problems and design systems, components, or processes that meet specified needs with appropriate consideration for public health and safety, cultural, societal, and environmental considerations.

Course Learning Outcome (CLO):

Upon successful completion of this course, the student will be able to:

NOTE:  Domain:           C = Cognitive,            

Assessment Tool: A = Assignment, Q = Quiz, M = Midterm, F = Final (P1: Part1)

Course Professional Outcome/ Industrial Usage:                         

                             This course is an introductory course on Digital Logic & Design. It is designed for students in engineering and other related fields. The purpose is to make students familiar with                                     modern hierarchy of digital hardware and explain them the state-of-the-art computer hardware design methodologies.

Course Outline and

Sessions Breakdown:  

                                    I. Number Systems & Boolean Algebra (CLO-1)

                                    (08 Sessions)

                                    Digital System, Binary Numbers, Number base Conversions, Octal and                                 Hexadecimal Numbers, Compliments, Signed Binary Number, Binary                                  Codes, Gray Code, BCD System, Binary Addition, Subtraction, and                             Multiplication. Introduction. basic definitions, Axiomatic definition                               of Boolean Algebra, Basic Theorems & Postulates. Boolean Function,                           Boolean laws and reduction, Conical Standard from and Digital Logic                         Gates.

                                    II Gate level Minimization (CLO 2,3)

                                    (08 Sessions)

                                    K-map (two variable, three variable and four variable), Prime                                                 Implicants, Sum of Product (SOP) & Product of Sum (POS)                                      Simplification. K-map Methods, NAND & NOR implementation,                                              Two level Implementations, & Don't Care Condition.

                                    III.  Combinational Logic Circuit, Design (CLO 3)

                                    (8 Sessions)

                                    Combinational Logic Circuit, Analysis Procedure, Design Procedure of                                       Combinational Logic Circuit. Binary Adder- Subtractors &Full Adder.                               Magnitude Comparator, Decoder, Encoder.          Implementation of full                                    adder with a decoder. Multiplexers and De-multiplexer.

                                    IV.  Synchronous Sequential Logic & Register & Counters:

                                    (08 Sessions) (CLO 3)

                                    Design and Analysis Procedure of Sequential circuits, Introduction                            sequential circuits, storage element: Latches. Registers, Shift Registers,                                   Synchronous & A-Synchronous counters.

Computer Usage:         Verilog HDL (ModelSim).

Projects /

Design Activities:         Students will be asked to design/solve complex engineering problem

Evaluation Criteria:    1. Assignments                         15%

2. Quizzes                                 15%

3. Mid-Term Exam                    20%

4. Final Exam                            50%

COURSE DISTRIBUTION ON WEEKLY BASIS

Policies

1. No makeup tests or quizzes, except in case of emergency, e.g. illness and accident. For makeup tests, medical certificate is required, and the instructor must be notified in advance of the test.
2. No late assignment will be accepted.